In many electronic circuit applications, including, for example, digital logic circuitry, power is applied to a previously unpowered or sleeping circuit during a “power-up” phase, wherein the voltage (e.g., VDD) supplied to the circuit is generally increased from zero volts to a nominal operating value. During this power-up phase, it is often desirable and/or necessary to reset certain circuit elements, such as, for example, logic flip-flops, etc., to some known logical state, so as to initialize the circuit until the power supply voltage VDD attains a sufficient level to sustain reliable operation of the circuit. In order to accomplish this, a power-up reset (PUR) signal is generated during the power-up phase. This PUR signal, which is applied to appropriate control inputs of select circuit elements, is designed to hold the selected circuit elements in an initial or reset state until the power supply reaches a predetermined threshold voltage level. In this manner, the circuit can begin operation in a predictable logical state.
A PUR circuit is typically employed to generate the PUR signal for resetting the select circuit elements. One requirement of the PUR signal is that it must remain active beyond the time necessary for the power supply voltage to fully stabilize, so as to provide ample time for the select circuit elements to be properly reset. In some conventional methodologies for generating a PUR signal, a PUR circuit is employed which is only active for a fixed amount of time as measured from the point at which the supply starts ramping from zero. As shown in FIG. 1, this standard PUR circuit, which is generally referred to as a transient sensing PUR circuit, typically includes a resistor R1 and a capacitor C1 coupled to the input of an inverter I1 for setting a fixed time constant during which the PUR signal RST is asserted. The PUR signal generated by a transient sensing PUR circuit is dependent on a ramp rate of the supply voltage. Unfortunately, power supplies typically have widely varying ramp rates. Thus, a disadvantage of the transient sensing approach is that the PUR circuit may, in some instances, undesirably remove the PUR signal before the power supply voltage has fully stabilized, particularly when the power supply exhibits a slowly increasing ramp.
Other conventional PUR circuits, as shown in FIG. 2 and described, for example, in U.S. Pat. No. 6,204,704 to Williams et al., generate a PUR signal based on fixed direct current (DC) voltage levels for the supply voltage. Such circuits may be referred to as voltage level sensing PUR circuits. In the voltage level sensing PUR circuit depicted in FIG. 2, a PMOS transistor M1 is employed having a source terminal (S) connected to the supply voltage VDD, a gate terminal (G) connected to VSS, and a drain terminal (D) connected to VSS through a series resistor R1. An inverter I1 having an input connected to the drain terminal of M1 generates a reset signal RST as an output of the PUR circuit. However, while the voltage level sensing PUR circuit is essentially independent of the supply voltage ramp rate, this PUR circuit fails to take into consideration variations in certain process, voltage and/or temperature (PVT) conditions of the circuit, and thus, like the transient sensing PUR circuit, may undesirably remove the PUR signal before the supply voltage has fully stabilized.
There exists a need, therefore, for improved techniques for generating a PUR signal that does not suffer from one or more of the problems exhibited by conventional PUR circuitry.